How Decoupled Capacitance can be Obtained without Components?
The goal is designing PCBs is to make them for the least amount of money while designing the best ways for them to perform well. Most people would say you cannot have both goals. However, new technological developments are helping engineers realize this goal by improving the high frequency electromagnetic interference performance and the quality of the design and at the same time keep costs down.
This technology is called Buried Capacitance. It is both patented and licensed across the world. It uses ZBC-2000 laminate material. In brief, it is a PCB producing methodology that spreads decoupled capacitance by inserting them in tiny dielectric layers inside the PCB and next to the power areas. This methodology essentially eliminates the need for decoupling capacitors. What this does is free up more space on the PCB and it helps designers make PCBS that have greater performance, or the same performance in a smaller board size.
Desired Buried Capacitance Examples
The diagrams inserted below give the popular ways that Buried Capacitance can be used. If you need more information, you can get it from your board producer.
Via in Pads and BGA
Via is a pad with a small plated hole in a Printed Circuit Board (PCB) which serves as a connection between copper tracks on various layers of a PCB. There are two types of micro vias used on multi-layered and high density PCBs, blind vias that can only been seen on one side and buried vias which are invisible. Devices and components with very fine pitches are now vastly used in addition to smaller size of PCBs which has created advanced challenges. A recent technology of PCB manufacturing with a self-describing name “via in pad” is the modern answer to these challenges.
The “via in pad” technique is primarily used to lower inductance, for using packages with finer pitch and for high-density designs. As suggested by its name, vias are placed directly under the pads of a component which provides more space for routing and increases density. Space in PCB is saved, for example: four components are placed by conventional fan-out whereas six are placed in the same space by using via in pad.
A trade-off to get intermediate cost with intermediate density as compared to buried or blind vias is filled via in pad. Listed below are some important benefits of using “via in pad” technique:
Fine pitch BGAs with lesser fan out (less than 0.75mm)
Close component spacing requirements can be met
Has improved thermal management
High speed PCB design has its own constraints, such as lesser inductance which can be handled
Component location do not require vias to be plugged in
A straight surface is provided for components where they can be easily placed
Despite many pros, this technique has some cons. A new technology is always increases the cost of a product. The two key cost increasing factors studied by PCB vendors were the increased complexity in manufacturing process as well as the cost of the material used in the conductive fill.
Cost of via fill is directly proportional to the number of vias in a design and their sizes, additionally board manufacturing process increases by almost 8 to 10 stages. This increases cost and complexity which can be compensated by the reduction of layers in the design which ultimately reduces the cost of the process.
FR-4 Prepreg/Bonding Stage Material Description and Dimension
To produce multiplayer PCBs a bonding material called prepreg or B-stage is utilized. B-stage bonding material types such as 106, 1080, 2113, 2116 and 7628 glass styles are employed by many board fabricators.
Base materials are the same as the prepreg properties after the full cure process.
The number of plies and the types of prepreg that can be used between each board layer have some limitations. Therefore, it is critical to confer with the application engineers of your PCB fabrication company to learn about these limitations.
Similar types of prepreg thickness dimensions include GETEK®, Rogers®, FR-406 and FR-408. To obtain the exact prepreg thickness information, confer with the application engineer of your PCB board fabricator.
How to Control Impedance
The transmission line’s characteristic impedance depends on how the width of a conductor, the thickness of a conductor, the thickness of the dielectric between the conductor and the ground power reference planes, as well as the dielectric constant of the dielectric medium relate to one another.
During the beginning stage of design, it is suggested that the client contact Bittele Electronics to discuss the impedance requirements. This discussion will provide a platform of communication for all parties to ensure the specifications and effects of material characteristics, including specific DKs and production processes, will have on the project’s impedance requirements and tolerances.
To determine the real impedance may require building a small prototype in order to test it. This is usually required due to the close impedances necessary in a design. It may also be necessary when a design has small line widths and dielectric thicknesses that have greater sensitivity to changes. For instance, a tolerance change from variation in etching have more significance for a 0.125 mm (0.005 inch) line width than for a 0.25 mm (0.100 inch) line.
Document the reference dimensions for line width and dielectric thickness only. This permits Bittele Electronics to make small changes to the line width and dielectric thickness to correspond to impedance goals.
Note: When it is needed to make a modification of a line width, it needs to be done to all of the lines of the same width in a particular layer. The client must give permission to make this type of modification.
Consider the importance of the Etch Factor when making impedance calculations.
The Etch Factor is the resultant reduction of a line width during the etching process. However, it is not necessary to consider the Etch Factor for PCBs that possess an Aspect Ratio GE 4.5:1 or boards that are GE 2.3 mm (0.093 inch) thick and have an Aspect Ratio of GE 3:1.
The suggested tolerance for impedance is +/- 10 percent. A smaller tolerance is usually attainable, particularly with complete embedded micro-strip and strip-line structures. Discuss this specification with Bittele Electronics for the best results.